ACD82224 Datasheet, PDF (10/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

Under normal operating conditions, the ACD82224 expects a received frame to have a minimum
inter frame gap (IFG). The minimum IFG required by the ACD82224 is 64 BT.
If a packet comes with an IFG less than 64 BT, the ACD82224 will not guarantee the reception of
that frame. The packet may be dropped if it is not properly received.
The ACD82224 will check all received frames for errors such as symbol error, FCS error, short
event, runt, long event, jabber, etc. Frames with any kind of error will not be forwarded to any
port.
Preamble Bit Processing
The preamble bit in the header of each frame will be used to synchronize the MAC logic with the
incoming bit stream. There is no limit on the minimum length or the maximum length of
preamble bits. After the receive-signal CRS_DV is asserted by the external PHY device, the
MAC will wait for the SFD pattern (10101011) to trigger a frame receiving process.
Destination Address Processing
As a frame comes in, the embedded Destination Address (DA) is passed to the Address
Resolution Logic (ARL). The ARL will compare it with the MAC address entries stored in the
address lookup table. A destination port is identified if a match of address is found. If external
ARL is used, the ACD82224 will indicate the present of 48-bit DA through the ARL interface. The
external ARL will use the value of DA for address comparison and return a result to the
ACD82224.
Source Address Processing
As a frame comes in, the embedded Source Address (SA) will be passed to the ARL. At the end
of the frame, if no error is detected, the SA will be used to update the address lookup table. If an
external ARL is used, the ACD82224 will indicate the presence of a SA on the ARL interface, so
that the external ARL can learn the address. The address table will be cleared after a Hardware-
Reset, but a Software-Reset will not clear the address table.
Frame Data
Frame data are transparent to the ACD82224. The ACD82224 will forward the data to destination
port(s) without interpreting the content of the frame data field.
FCS Calculation
Each port of the ACD82224 has a CRC checking logic to verify if the received frame has the
correct FCS value. An incorrect FCS value is an indication of a fragmented frame or a frame
with frame bit error. The method of calculating the CRC value is by using the following
polynomial,
32
26
23
22
16
12
11
10
8
7
5
4
2
G(x) = x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1
as a divider to divide the bit sequence of the incoming frame, beginning with the first bit of the
destination address field, to the end of the data field. The result of the calculation, which is the
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