ACD82224 Datasheet, PDF (23/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

Table-6.8: ZBT SRAM Interface
Name
DATA[47:0]
BE[2:0]
EOF
ADDR[18:0]
nWE
Type
I/O
I/O
I/O
O
O
nCE
O
Description
Memory data bus
Byte enable
End of frame
Memory address bus
Write enable:
0=Write
1=Read
Chip enable, low active
The synchronous clock input of the External SRAM’s should connect to 100 MHz system clock.
Data is written into the SRAM or read from the SRAM in 52-bit wide words. ADDRx specifies the
address of each word.
• DATA[47:0] are used to transfer up to 6 octets of data each time.
• BE[2:0] indicate the valid bytes in 6 octet of data in DATA[47:0].
• EOF indicates the last word of a frame.
• ADDR[18:0] specifies up to 512K word addresses.
• nWE specifies the type of operation for each clock cycle.
• nCE selects the SRAM chip associated with the word address.
The timing requirement for SRAM access is described in the chapter of “Timing Description.”
ARL & MIB Interfaces
The ARL interface provides a communication path between the ACD82224 and an external ARL
device such as the ACD80800, which can provide up to 11K of address lookup. The MIB
interface provides a communication path between the ACD82224 and an external MIB device
such as the ACD80900 for management function implementation. Both the ACD80800 and the
ACD80900 collect traffic information by monitoring the data bus of the buffer memory. The two
interfaces share many common pins, as shown in Figure-6.1and Table-6.9.
When the ACD82224 receives a frame, it will store it into the frame buffer memory through data
bus DATA[47:0]. The external ARL extracts the destination address and source address of the
frame posted on the Data [0:47] while it is written into the memory. It then finds the
corresponding destination port and returns the result through the ARLDI[3:0] lines to the
ACD82224. The timing requirement on ARL signals is described in Chapter 9, “Timing
Description”. At the same time, the external MIB also grabs the frame into its internal buffer for
further management processing. Please see the ACD80800 and the ACD80900 Data Sheets for
details.
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