ACD82224 Datasheet, PDF (31/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

SAL & SAH register (register 8,9)
The SAL and SAH registers together contain the complete Source Address for pause frame
generation. SAL contains the least significant 24 bit of the MAC address. SAH contains the most
significant 24 bit of the MAC address. The default locally managed source address for pause
frame generation is FEh-FFh-FFh-FFh-FFh-FFh a. Table-7.8 and table-7.9 describes all the bits
of these two registers.
Table-7.8: SAL Register
Bit
Description
7:0
Bit 47:40 of the switch’s MAC address.
15:8
Bit 39:32 of the switch’s MAC address.
23:16
Bit 31:24 of the switch’s MAC address.
Default
FEh
FFh
Table-7.9: SAH Register
Bit
Description
7:0
Bit 23:16 of the switch’s MAC address.
15:8
Bit 15:8 of the switch’s MAC address.
23:16
Bit 7:0 of the switch’s MAC address.
Default
FFh
UTH register (register 10)
The UTH register contains the unicast buffer thresholds for each port. When the upper threshold
is exceeded, the MAC may generate a Max-Pause-Frame. When the lower threshold is crossed,
the MAC may generate a Mini-Pause-Frame. Table-7.10 describes each bit in this register.
Table-7.10: UTH Register
Bit
Description
7:0
Lower threshold of unicast utilization.
15:8
Higher threshold of unicast utilization.
Total Frame Buffer
Depth (52-bit wide
word)
64K
128K
256K
512k
64K
128K
256K
512k
Default*
2
4
8
16
4
8
24
64
*_{Note: The value is related to the memory size specified by bit[9:8] of register 25.}
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