ACD82224 Datasheet, PDF (20/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

RMII Interface (RMII)
The ACD82224 communicates with the external 10/100 Ethernet transceivers through standard
RMII interface. The signals of RMII interface are described in Table-6.2a:
Table-6.2a: RMII Interface
Name
PxCRSDV
PxRXD0
PxRXD1
PxTXEN
PxTXD0
PxTXD1
RMIICLK[5:0]
Type
I
I
I
O
O
O
O
Description
Carrier Sense/Receive data valid
Receive data bit 0
Receive data bit 1
Transmit enable
Transmit data bit 0
Transmit data bit 1
Reduced MII clock (50 MHz)
For RMII interface, signal PxRXDV, PxRXD0, and PxRXD1 are sampled by the rising edge of
RMIICLK. Signal PxTXEN, PxTXD0, and PxTXD1 are clocked out by the falling edge of
RMIICLK. The detailed timing requirement is described in the chapter of “Timing Description”
MII Interface (MII)
The last port (e.g. Port-23 on the ACD82224) can be selected to act in MII mode. The MII mode
is used to connect the ACD80900 for in-band management function. The ACD80900 acts as a
three-way switch to allow the management CPU to share the regular port. The signals of MII
interface are described in Table-6.2b:
Table-6.2b: MII Interface
MII Mode
RMII Mode
P23CRS
P23CRSDV
P23RXDV
NC
P23RXCLK
NC
P23RXERR
NC
P23RXD0
P23RXD0
P23RXD1
P23RXD1
P23RXD2
NC
P23RXD3
NC
P23COL
NC
P23TXEN
P23TXEN
P23TXCLK
NC
P23TXD0
P23TXD0
P23TXD1
P23TXD1
P23TXD2
NC
P23TXD3
NC
Type
I
I
I
I
I
I
I
I
I
O
I
O
O
O
O
Description
Carrier sense
Receive data valid
Receive clock (25/2.5 MHz)
Receive error
Receive data bit 0
Receive data bit 1
Receive data bit 2
Receive data bit 3
Collision indication
Transmit data valid
Transmit clock (25/2.5 MHz)
Transmit data bit 0
Transmit data bit 1
Transmit data bit 2
Transmit data bit 3
Under the MII mode, signal P23RXDV, P23RXER and P23RXD0 through P23RXD3 are sampled by the
rising edge of P23RXCLK. Signal P23TXEN, and P23TXD0 through P23TXD3 are clocked out by the
falling edge of P23TXCLK. The detailed timing requirement is described in the chapter of “Timing
Description”
PHY Management Interface
All control and status registers of the PHY devices are accessible through the PHY management
interface. The interface consists of two signals: MDC and MDIO, which are described in table-6.3.
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