ACD82224 Datasheet, PDF(67/77 Page) List of Unclassifed Manufacturers

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ACD82224 Datasheet, PDF (67/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

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4. INTERFACE DESCRIPTION

CPU Interface

The CPU can communicate with the ARL through the UART interface of the switch controller.

The management CPU can send commands to the ARL by writing into associated registers, and

retrieve result from the ARL by reading out of the corresponding registers. The registers are

described in the section on âRegister Description.â The CPU interface signals are described by

table-1:

Table-1: CPU Interface

Name

I/O

UARTDI

UARTDO

Description

UART input data line.

UART output data line.

UARTDI is used by the control CPU to send commands into the ARL. The baud rate will be

automatically detected by the ARL. The result is returned through the UARTDO line with the

detected baud rate. The format of the command packet is shown as follows:

A command sent by the CPU through the CPUDI line consists of 7 octets. Command frames

transmitted on CPUDI have the format shown below:

ARL CPUDI Format

Operation

Command

Write

0100XX11

Read

0100XX01

Address

A[7:0]

Data

D[31:0]

Checksum

C[7:0]

The byte order of data in all fields follows the big-endian convention, i.e. most significant octet

first. The bit order is the least significant order first.

The Command octet specifies the type of the operation. The Bit-7, bit-6, and bit-5 of the

command octet are specified the Device Type.

(1) Switch Controller, the device type is 001.

(2) ARL Controller, the device type is 010.

(3) Management Controller, the device type is 100.

The Bit-2, and bit-3 of the command octet are used to specify the device ID of the chip which is

shared with ACD82224 device ID (ACD82224 bit 20 and bit 21 of Register 25).

The address octet specifies the number of the register.

For write operation, the Data field is a 4-octet value to specify what to write into the register.

For read operation, the Data field is a 4-octet 0 as padded data. If the data of register is less than

32-bit, it is align to bit-0 of Data field.

The checksum value is an 8-bit value of exclusive-OR of all octets in the frame, starting from the

Command octet.

For each valid command received, the ARL will always send a response. Response from the

ARL is sent through the CPUDO line. Response frames sent by the ACD82224 have the

following format:

ARL UARTDO (Response) Format

Response