ACD82224 Datasheet, PDF (43/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

P13CRS_DV R24
P13RXD0
N23
P13RXD1
N26
P13TXD0
R23
P13TXD1
P26
P13TXEN
P25
P14CRS_DV M26
P14RXD0
L25
P14RXD1
M24
P14TXD0
M25
P14TXD1
N24
P14TXEN
P24
P15CRS_DV L24
P15RXD0
K26
P15RXD1
K23
P15TXD0
M23
P15TXD1
K25
P15TXEN
L26
P16CRS_DV G25
P16RXD0
H23
P16RXD1
G26
P16TXD0
H26
P16TXD1
J24
P16TXEN
K24
P17CRS_DV F26
P17RXD0
G24
P17RXD1
E25
P17TXD0
F25
P17TXD1
G23
P17TXEN
H24
P18CRS_DV E23
P18RXD0
D26
P18RXD1
C25
P18TXD0
F24
P18TXD1
D25
P18TXEN
E26
P19CRS_DV B24
P19RXD0
A24
P19RXD1
B23
P19TXD0
C26
P19TXD1
A25
Page 42 of 77
POS REG Bit-20: 2-bit device ID bit-0 for UART
communication. ACD82224 responses only to UART
commands with matching ID.
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
O
Transmit enable
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
I/O* Transmit enable (default low)
POS REG Bit-21: 2-bit device ID bit-1for UART communication.
The device responses only to UART commands with matching
ID.
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
I/O* Transmit Enable (default low)
POS REG Bit-19: system will start by itself upon hardware
reset
System will not start until bit-5/6 of register-16 is set .
I
Carrier Sense/Receive Data Valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
O
Transmit enable
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
I/O* Transmit data bit 0 (default low)
POS REG Bit-4 ZBT SRAM Clock Timing Adjustment Bit-0
I/O* Transmit data bit 1 (default low)
POS REG Bit-5: ZBT SRAM Clock Timing Adjustment Bit-1
I/O* Transmit enable (default low)
POS REG Bit-10: Reserved
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
I/O* Transmit data bit 0 (default low)
POS REG Bit-6: ZBT SRAM Clock Timing Adjustment Bit-2
I/O* Transmit data bit 1 (default low)
POS REG Bit-7: ZBT SRAM Clock Timing Adjustment Bit-3
I/O* Transmit enable
POS REG Bit-11: Long Event Defined As Frame Longer Than
1518/1530 Byte (default high)
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
Confidential
Page 42