ACD82224 Datasheet, PDF (42/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

P05TXD1
P05TXEN
AF19
AF18
P06CRS_DV
P06RXD0
P06RXD1
P06TXD0
P06TXD1
P06TXEN
AF21
AD20
AE22
AD19
AE21
AF20
P07CRS_DV
P07RXD0
P07RXD1
P07TXD0
P07TXD1
P07TXEN
P08CRS_DV
P08RXD0
P08RXD1
P08TXD0
P08TXD1
P08TXEN
AC22
AF23
AD22
AD21
AE23
AF22
AD25
AD26
AC25
AF24
AE26
AD23
P09CRS_DV
P09RXD0
P09RXD1
P09TXD0
P09TXD1
P09TXEN
AB23
AB24
Y23
AC26
AB25
AC24
P10CRS_DV
P10RXD0
P10RXD1
P10TXD0
P10TXD1
P10TXEN
P11CRS_DV
P11RXD0
P11RXD1
P11TXD0
P11TXD1
P11TXEN
Y26
Y24
W25
AA26
Y25
AA24
V25
V26
U25
W26
W24
V23
P12CRS_DV U24
P12RXD0
R25
P12RXD1
R26
P12TXD0
U23
P12TXD1
T25
P12TXEN
U26
Page 41 of 77
ERRMSK REG Bit-6 (default high)
I/O* Transmit data bit 1
ERRMSK REG Bit-7 (default high)
I/O* Transmit enable (default Low)
CLKADJ REG Bit-4: Write Data Window Width Adjustment bit-
0
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
I/O* Transmit enable (default low)
CLKADJ REG Bit-5: Write Data Window Width Adjustment bit-
1
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
O
Transmit enable
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
I/O* Transmit enable
CLKADJ REG Bit-6: Write Data Window Location Adjustment.
bit-0 (default low)
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
I/O* Transmit enable
CLKADJ REG Bit-7: Write Data Window Location Adjustment.
bit-1 (default low)
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
O
Transmit enable
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
I/O* Transmit enable
POS REG Bit-23: RMII RX’s data is latched on falling
edge/rising edge(default high), Suggest pull-low with 4.7K
resister.
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
I/O* Transmit enable (default low)
Confidential
Page 41