CO4011A-FL Datasheet, PDF (6/37 Pages) List of Unclassifed Manufacturers – Single Chip CANopen Controller for Remote I/O

CO4011A-FL
Single Chip CANopen Controller for Remote I/O
Device Configuration
The following sections describe the device con-
figuration with meaning:
1: ViH logic high level
0: ViL logic low level
CAN Identifier
The CAN Identifier will be set with Pins ID0 to ID6.
This configuration pins use internal inverter. The ID
is set as follows:
ID6 ID5 ID4 ID3 ID2 ID1 ID0 CAN-Identifier
1 1 1 1 1 1 1 Programmable ID
1 1 1 1 1 1 0 1 = 0x01
1 1 1 1 1 0 1 2 = 0x02
1 1 1 1 1 0 0 3 = 0x03
1 1 1 1 0 1 1 4 = 0x04
….
….
1 0 0 0 0 0 0 63 = 0x3F
0 1 1 1 1 1 1 64 = 0x40
0 1 1 1 1 1 0 65 = 0x41
….
….
0 0 0 0 0 1 0 125 = 0x7C
0 0 0 0 0 0 1 126 = 0x7E
0 0 0 0 0 0 0 127 = 0x7F
All Identifiers from 1 to 127 are valid settings.
Identifier 0 is used to load the ID from object 2100.
Baud rate
The baud rate configuration will be done with con-
figuration inputs BD0 to BD2
BD2 BD1 BD0 CAN-Baud Rate / Bus length
1 1 1 1 Mbit/sec 25 m *1)
1 1 0 800 kbit/sec 50 m *1)
1 0 1 500 kbit/sec 100 m *2)
1 0 0 250 kbit/sec 250 m *2)
0 1 1 125 kbit/sec 500 m *3)
0 1 0 50 kbit/sec 1000 m *3)
0 0 1 20 kbit/sec 2500 m *3)
0 0 0 10 kbit/sec 5000 m *3)
*1) Calculation without optocouplers.
For optocouplers bus length is reduced for about
4m per 10 nsec propagation delay of employed
optocoupler type
*2) Calculation with 40 nsec optocoupler
propagation delay
*3) Calculation with 100 nsec optocoupler
propagation delay
The calculation of the bus length is based on a line
propagation delay of 5 nsec/m.
Analog Input Selection
With configuration bits CFG0 and CFG1 the number
and resolution of analog inputs are set.
CFG CFG Nr of
1 0 analog
channels
11
0
10
8
01
4
00
Reso- Analog Digital
lution Inputs Inputs
-
-
8 Bit IN0 to
*1)
IN7
10 Bit IN 0 to
*2)
IN 3
Reserved
IN0 to
IN11
IN8 to
IN11
IN4 to
IN11
*1) The analog inputs are mapped as unsigned 8
values into a single transmit PDO (TPDO2).
*2) The analog inputs are mapped as signed 16
values into one transmit PDO (TPDO2.
If analog inputs are enabled, the corresponding input
channels are not scanned for digital signals. The
digital input signals for those channels are always
set to 0 without taking care of the analog input level.
If analog inputs are disabled (CFG1 = 1, CFG0 = 1)
the analog input voltage of input IN0 to IN3 is not
scanned.
Do not apply higher voltages than VCC and AVCC to
any input pin. If the A/D converter is not used,
connect the power supply pins as follows:
AVCC = AVREF = VCC, AVSS = VSS.
Configuration of IO-Port
Device pins IO0 to IO7 may be used as digital inputs
or digital outputs. This selection must be done with
CFG2.
See also section "Mapping I/O to Object Dictionary"
for additional information
CFG2 I/O Port is used for
1 Digital Input
0 Digital Output
Enable additional CAN features
With setting CFG3 to 0 the following special features
may be enabled:
- Easy Mapping of Objects to PDO
CFG3 I/O Port is used for
1 Normal operation mode
0 Enable additional features.
These features might be incompatible with CANopen
conformance
Test.
frenzel + berg elektronik – Maximilianstr. 28 – 89231 Neu-Ulm – Germany - phone [phone] - fax [phone] – www.frenzel-berg.de
Page 6 of 6
Revision 1.39
May/19/2003