LM3S8962 Datasheet, PDF (545/620 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8962 Microcontroller
The positional counter is automatically reset on one of two conditions: sensing the index pulse or
reaching the maximum position value. Which mode is determined by the ResMode bit of the QEI
Control (QEICTL) register.
When ResMode is 0, the positional counter is reset when the index pulse is sensed. This limits the
positional counter to the values [0:N-1], where N is the number of phase edges in a full revolution
of the encoder wheel. The QEIMAXPOS register must be programmed with N-1 so that the reverse
direction from position 0 can move the position counter to N-1. In this mode, the position register
contains the absolute position of the encoder relative to the index (or home) position once an index
pulse has been seen.
When ResMode is 1, the positional counter is constrained to the range [0:M], where M is the
programmable maximum value. The index pulse is ignored by the positional counter in this mode.
The velocity capture has a configurable timer and a count register. It counts the number of phase
edges (using the same configuration as for the position integrator) in a given time period. The edge
count from the previous time period is available to the controller via the QEISPEED register, while
the edge count for the current time period is being accumulated in the QEICOUNT register. As soon
as the current time period is complete, the total number of edges counted in that time period is made
available in the QEISPEED register (losing the previous value), the QEICOUNT is reset to 0, and
counting commences on a new time period. The number of edges counted in a given time period
is directly proportional to the velocity of the encoder.
Figure 20-2 on page 545 shows how the Stellaris^® quadrature encoder converts the phase input
signals into clock pulses, the direction signal, and how the velocity predivider operates (in Divide
by 4 mode).
Figure 20-2. Quadrature Encoder and Velocity Predivider Operation
PhA
PhB
clk
clkdiv
dir
pos -1 -1 -1 -1 -1 -1 -1 -1 -1
rel +1
+1
+1
+1 +1 +1 +1 +1 +1 +1 +1
+1
+1
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+1
+1
+1
The period of the timer is configurable by specifying the load value for the timer in the QEILOAD
register. When the timer reaches zero, an interrupt can be triggered, and the hardware reloads the
timer with the QEILOAD value and continues to count down. At lower encoder speeds, a longer
timer period is needed to be able to capture enough edges to have a meaningful result. At higher
encoder speeds, both a shorter timer period and/or the velocity predivider can be used.
The following equation converts the velocity counter value into an rpm value:
rpm = (clock * (2 ^ VelDiv) * Speed * 60) ÷ (Load * ppr * edges)
where:
clock is the controller clock rate
ppr is the number of pulses per revolution of the physical encoder
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CapMode set to 0 and
4 for CapMode set to 1)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder
is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of
September 02, 2007
545
Preliminary