LM3S8962 Datasheet, PDF (438/620 Pages) List of Unclassifed Manufacturers – Microcontroller

Controller Area Network (CAN) Module
Bit/Field
4
3
2
1
Name
Control
ClrIntPnd
TxRqst/NewDat
DataA
Type
R/W
R/W
R/W
R/W
Reset
0x0
0x0
0x0
0x0
Description
Access Control Bits
When WRNRD=1 (writes):
0: Control bits unchanged.
1: Transfer control bits to message object.
When WRNRD=0 (reads):
0: Control bits unchanged.
1: Transfer control bits to Message Buffer Register.
Clear Interrupt Pending Bit
Note: This bit is not used when in write (WRNRD=1).
0: IntPnd bit in CANIFnMCTL register remains unchanged.
1: Clear IntPnd bit in the CANIFnMCTL register in the message object.
Access Transmission Request or New Data
When WRNRD=1 (writes):
Access Transmission Request Bit
0: TxRqst bit unchanged.
1: Set TxRqst bit
Note:
If a transmission is requested by programming this TxRqst
bit, the parallel TxRqst in the CANIFnMCTL register is
ignored.
When WRNRD=0 (reads):
Access New Data Bit
0: NewDat bit unchanged.
1: Clear NewDat bit in the message object.
Note:
A read access to a message object can be combined with the
reset of the control bits IntPdn and NewDat. The values of
these bits that are transferred to the CANIFnMCTL register
always reflect the status before resetting these bits.
Access Data Byte 0 to 3
When WRNRD=1 (writes):
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 (CANIFnDA1 and CANIFnDA2) to message
object.
When WRNRD=0 (reads):
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 in message object to CANIFnDA1 and
CANIFnDA2.
438
September 02, 2007
Preliminary