LM3S8962 Datasheet, PDF (122/620 Pages) List of Unclassifed Manufacturers – Microcontroller

Hibernation Module
7.1 Block Diagram
Figure 7-1. Hibernation Module Block Diagram
XOSC0
XOSC1
WAKE
HIBCTL.CLK32EN
/128
HIBCTL.CLKSEL
Non-Volatile
Memory
HIBDATA
Pre-Divider
HIBRTCT
RTC
HIBRTCC
HIBRTCLD
HIBRTCM0
HIBRTCM1
Interrupts
HIBIM
HIBRIS
HIBMIS
HIBIC
MATCH0/1
LOWBAT
VDD
VBAT
Low Battery
Detect
Power
Sequence
Logic
HIBCTL.LOWBATEN
HIBCTL.PWRCUT
HIBCTL.RTCWEN
HIBCTL.EXTWEN
HIBCTL.VABORT
Interrupts
to CPU
HIB
7.2
7.2.1
Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off. The Hibernation module power is determined dynamically.
The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the
battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power
switch selects the appropriate voltage source. The Hibernation module also has a separate clock
source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external
voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the
internal RTC reaches a certain value. The Hibernation module can also detect when the battery
voltage is low, and optionally prevent hibernation when this occurs.
Power-up from a power cut to code execution is defined as the regulator turn-on time (specifed at
t_{HIB_TO_VDD} maximum) plus the normal chip POR (see “Hibernation Module” on page 585).
Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is t_{HIB_REG_WRITE}, therefore software
must guarantee that a delay of t_{HIB_REG_WRITE} is inserted between back-to-back writes to certain
Hibernation registers, or between a write followed by a read to those same registers. There is no
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September 02, 2007
Preliminary