LM3S8962 Datasheet, PDF (447/620 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8962 Microcontroller
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TxRqst bits of the 32 message objects. By
reading out these bits, the CPU can check which message object has a transmission request pending.
The TxRqst bit of a specific message object can be changed by three sources: (1) the CPU via the
CAN IFn Message Control (CANIFnMCTL) register, (2) the message handler state machine after
the reception of a Remote Frame, or (3) the message handler state machine after a successful
transmission.
The CANTXRQ1 register contains the TxRqst bit of the first 16 message objects in the message
RAM; the CANTXRQ2 register contains the TxRqst bit of the second 16 message objects.
CAN Transmission Request 1 (CANTXRQ1)
CAN0 base: 0x4004.0000
Offset 0x100
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TxRqst
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:16
15:0
Name
reserved
TxRqst
Type
RO
RO
Reset
0x0000
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmission Request Bits
(of all message objects)
0: The message object is not waiting for transmission.
1: The transmission of the message object is requested and is not yet
done.
September 02, 2007
447
Preliminary