LM3S8962 Datasheet, PDF (477/620 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8962 Microcontroller
Register 16: Ethernet MAC Timer Support (MACTS), offset 0x03C
This register enables software to enable timer support on the transmission and reception of frames.
This register is only applicable for devices that have 1588 hardware support; for all others, a read
returns 0s.
Ethernet MAC Timer Support (MACTS)
Base 0x4004.8000
Offset 0x03C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TSEN
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
TSEN
Type
RO
R/W
Reset
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Time Stamp Enable
When set, the TSEN bit multiplexes the TX and RX interrupts to the CCP
inputs of General-Purpose Timer 3.
17.6
MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers. All addresses given are
absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register
Descriptions” on page 459.
September 02, 2007
477
Preliminary