LM3S8962 Datasheet, PDF (376/620 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I²C) Interface
Figure 15-2. I²C Bus Configuration
SCL
SDA
RPUP RPUP
I2C Bus
I2CSCL I2CSDA
StellarisTM
SCL
SDA
3rd Party Device
with I2C Interface
SCL
SDA
3rd Party Device
with I2C Interface
15.2.1
I²C Bus Functional Overview
The I²C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris^®
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are high.
Every transaction on the I²C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 376) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
15.2.1.1
START and STOP Conditions
The protocol of the I²C bus defines two states to begin and end a transaction: START and STOP.
A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and
a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus
is considered busy after a START condition and free after a STOP condition. See Figure
15-3 on page 376.
Figure 15-3. START and STOP Conditions
SDA
SCL
START
condition
STOP
condition
SDA
SCL
15.2.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 15-4 on page 377. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
376
September 02, 2007
Preliminary