LM3S8962 Datasheet, PDF (489/620 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8962 Microcontroller
Bit/Field
5
4
3:2
1
0
Name
APOL
RVSPOL
reserved
PCSBP
RXCC
Type
R/W
R/W
RO
R/W
R/W
Reset
0
0
0
0
0
Description
Auto-Polarity Disable
When set, disables the PHY’s auto-polarity function.
If this bit is 0, the PHY automatically inverts the received signal due to
a wrong polarity connection during Auto-Negotiation if the PHY is in
10Base-T mode.
Receive Data Polarity
This bit indicates whether the receive data pulses are being inverted.
If the APOL bit is 0, then the RVSPOL bit is read-only and indicates
whether the auto-polarity circuitry is reversing the polarity. In this case,
a 1 in the RVSPOL bit indicates that the receive data is inverted while a
0 indicates that the receive data is not inverted.
If the APOL bit is 1, then the RVSPOL bit is writable and software can
force the receive data to be inverted. Setting RVSPOL to 1 forces the
receive data to be inverted while a 0 does not invert the receive data.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PCS Bypass
When set, enables the bypass of the PCS and scrambling/descrambling
functions in 100Base-TX mode. This mode is only valid when
Auto-Negotiation is disabled and 100Base-T mode is enabled.
Receive Clock Control
When set, enables the Receive Clock Control power saving mode if the
PHY is configured in 100Base-TX mode. This mode shuts down the
receive clock when no data is being received from the physical medium
to save power. This mode should not be used when PCSBP is enabled
and is automatically disabled when the LOOPBK bit in the MR0 register
is set.
September 02, 2007
489
Preliminary