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M14D128168A-2M Datasheet, PDF (8/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle
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ESMT
M14D128168A (2M)
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Symbol
-1.8
Min.
Max.
-2.5
Min.
Max.
Unit Note
Input High (Logic 1) Voltage VIH(AC) VREF + 0.2
VREF + 0.2
V
Input Low (Logic 0) Voltage
VIL(AC)
VREF - 0.2
VREF - 0.2
V
Input Differential Voltage
VID(AC)
0.5
VDDQ + 0.6
0.5
VDDQ
V
1
Input Crossing Point Voltage VIX(AC)
0.5 x VDDQ - 0.5 x VDDQ + 0.5 x VDDQ - 0.5 x VDDQ +
0.175
0.175
0.175
0.175
V
2
Output Crossing Point Voltage VOX(AC)
0.5 x VDDQ -
0.125
0.5 x VDDQ +
0.125
0.5 x VDDQ -
0.125
0.5 x VDDQ +
0.125
V
2
Note:
1. VID(AC) specifies the input differential voltage |VTR – VCP| required for switching, where VTR is the true input signal (such
as CLK,DQS) and VCP is the complementary input signal (such as CLK , DQS ). The minimum value is equal to VIH(AC) –
VIL(AC).
2. The typical value of VIX / VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX / VOX(AC) is
expected to track variations in VDDQ. VIX / VOX(AC) indicates the voltage at which differential input / output signals must
cross.
Input / Output Capacitance
Parameter
Input capacitance
(A0~A12, BA0~BA1, CKE, CS , RAS , CAS , WE , ODT)
Input capacitance (CLK, CLK )
DQS, DQS & Data input/output capacitance
Input capacitance (DM)
Note: 1. Maximum capacitance delta is 0.25 pF.
2. Maximum capacitance delta is 0.5 pF.
Elite Semiconductor Memory Technology Inc.
Symbol
CIN1
CIN2
CI / O
Min.
0.5
0.5
1.5
CIN3
0.5
Max.
1.5
1.0
3.5
Unit Note
pF 1
pF 1
pF 2
1.5
pF 2
Publication Date : Mar. 2013
Revision : 1.4
8/59
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