M14D128168A-2M Datasheet, PDF (29/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
ODT Timing for Power-Down Mode
T0
T1
T2
T3
T4
T5
CLK
CLK
CKE
tIS
tIS
ODT
Internal
Term Res.
tAONPD(min.)
tAONPD(max.)
tAOFPD(min.)
Rtt
T6
tAOFPD(max.)
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
29/59