M14D128168A-2M Datasheet, PDF(27/59 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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M14D128168A-2M Datasheet, PDF (27/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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ESMT

M14D128168A (2M)

Extended Mode Register Set-3 [EMRS(3)]

BA1 BA0

A12

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

BA1 BA0 Mode Register

0 0 MRS

0 1 EMRS(1)

1 0 EMRS(2)

1 1 EMRS(3): Reserved

Note:

EMRS(3) is reserved for future. All bits except BA0 and BA1 are reserved for future use and must be set to 0 when

setting to mode register during initialization.

Elite Semiconductor Memory Technology Inc.

Publication Date : Mar. 2013

Revision : 1.4

27/59

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