M14D128168A-2M Datasheet, PDF(36/59 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

M14D128168A-2M Datasheet, PDF (36/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

◁

ESMT

M14D128168A (2M)

Burst Write Operation

The Burst Write command is issued by having CS , CAS and WE LOW while holding RAS HIGH at the rising edge of the

clock (CLK). The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL)

minus one and is equal to (AL + CL -1); and is the number of clocks of delay that are required from the time the write command is

registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS) should be driven low (preamble) one

clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS

following the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge

during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed,

which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal

is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the

write recovery time (tWR).

Write (Data Input) Timing

DQS

tWPRE

tDQSH

tDQSL

Din0

tDS

Din1

tDS

Din2

tDH

tWPST

Din3

tDH

Burst Write

< RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 >

CLK

CMD

Posted CAS

WRITE A

NOP

Case1 : with tDQSS(max)

DQS,DQS

WL = RL -1 = 4

DQs

Case2 : with tDQSS(min)

DQS,DQS

WL = RL -1 = 4

DQs

NOP

Precharge

tDQSS

tDSS

DinA0 DinA1 DinA2 DinA3

tDQSS tDSH

DinA0 DinA1 DinA2 DinA3

>= tWR

< RL= 3 (AL= 0; CL= 3); WL= 2; BL= 4 >

CLK

CMD

WRITE A NOP

NOP

Precharge

NOP

Bank A

Active

tDQSS

DQS,DQS

WL = RL -1 = 2

tWR

DQs

DinA0 DinA1 DinA2 DinA3

>= tRP

Elite Semiconductor Memory Technology Inc.

Publication Date : Mar. 2013

Revision : 1.4

36/59

▷