M14D128168A-2M Datasheet, PDF (4/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Ball Description
Pin Name
A0~A12,
BA0,BA1
DQ0~DQ15
RAS
CAS
WE
V_SS
V_DD
DQS, DQS
(LDQS, LDQS
UDQS, UDQS )
ODT
NC
Function
Address inputs
- Row address A0~A11
- Column address A0~A8
A12: use for MRS/EMRS
A10/AP : Auto Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Command input
Command input
Command input
Ground
Power
Bi-directional differential Data Strobe.
LDQS and /LDQS are DQS for DQ0~DQ7;
UDQS and /UDQS are DQS for DQ8~DQ15.
On-Die-Termination.
ODT is only applied to DQ0~DQ15, DM, DQS
and /DQS.
No connection
Pin Name
Function
DM
(LDM, UDM)
DM is an input mask signal for write data.
LDM is DM for DQ0~DQ7 and UDM is DM
for DQ8~DQ15.
CLK, CLK
CKE
CS
V_DDQ
V_SSQ
V_REF
Differential clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
Reference Voltage
V_DDL
Supply Voltage for DLL
V_SSDL
Ground for DLL
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V_SS
Voltage on V_DD supply relative to V_SS
Voltage on V_DDL supply relative to V_SS
Voltage on V_DDQ supply relative to V_SS
Storage temperature
Symbol
V_IN, V_OUT
V_DD
V_DDL
V_DDQ
T_STG
Value
-0.5 ~ 2.3
-1.0 ~ 2.3
-0.5 ~ 2.3
-0.5 ~ 2.3
-55 ~ +100
Unit
V
V
V
V
°C ( Note *)
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Note *: Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
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