M14D128168A-2M Datasheet, PDF (12/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
AC Timing Parameter & Specifications - Continued
Parameter
Symbol
-1.8
Min.
Active to Precharge command
Active to Active command
(same bank)
t_RAS
40
t_RC
53.125
Auto Refresh row cycle time
Active to Read, Write delay
Precharge command period
Active bank A to Active bank B
command (1KB page size)
t_RFC
75
t_RCD
13.125
t_RP
13.125
t_RRD
7.5
Four activate window (1KB page size) t_FAW
35
Write recovery time
t_WR
15
Write data in to Read command delay t_WTR
7.5
Col. address to Col. address delay
t_CCD
2
Average periodic Refresh interval
( 0℃ ≦T_C ≦ +85℃ )
t_REFI
Average periodic Refresh interval
(+85℃ ＜T_C ≦ +95℃)
Write preamble
Write postamble
DQS Read preamble
DQS Read postamble
Load Mode Register / Extended Mode
Register cycle time
t_REFI
t_WPRE
t_WPST
t_RPRE
t_RPST
t_MRD
0.35
0.4
0.9
0.4
2
Auto Precharge write recovery +
Precharge time
t_DAL
WR + tn_RP
Internal Read to Precharge command
delay
t_RTP
7.5
Exit Self Refresh to Read command
Exit Self Refresh to non-Read
command
t_XSRD
t_XSNR
200
t_RFC + 10
Exit Precharge Power-Down to any
non-Read command
t_XP
3
Exit Active Power-Down to Read
command
Exit active power-down to Read
command
(slow exit / low power mode)
CKE minimum pulse width
(high and low pulse width)
Minimum time clocks remains ON
after CKE asynchronously drops low
t_XARD
t_XARDS
t_CKE
t_DELAY
3
10 - AL
3
t_IS +
t_CK(avg)+t_IH
Max.
70K
15.6
7.8
0.6
1.1
0.6
M14D128168A (2M)
-2.5
Min.
Max.
45
70K
57.5
75
12.5
12.5
7.5
35
15
7.5
2
15.6
7.8
0.35
0.4
0.6
0.9
1.1
0.4
0.6
2
WR + tn_RP
7.5
200
t_RFC + 10
2
2
8 - AL
3
t_IS +
t_CK(avg)+t_IH
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_CK
μs
μs
t_CK (avg)
t_CK (avg)
t_CK (avg) 10
t_CK (avg) 11
t_CK
t_CK
18
ns
t_CK
ns
t_CK
t_CK
2
t_CK
1,2
t_CK
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
12/59