M14D128168A-2M Datasheet, PDF(45/59 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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M14D128168A-2M Datasheet, PDF (45/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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ESMT

M14D128168A (2M)

Auto Refresh & Self Refresh

Auto Refresh

An Auto Refresh command is issued by having CS , RAS and CAS held LOW with CKE and WE HIGH at the rising edge of the

clock(CLK). All banks must be precharged and idle for tRP(min) before the Auto Refresh command is applied. An address counter,

internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once

this cycle has started. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh

command and the next Bank Active command or subsequent Auto Refresh command must be greater than or equal to the

tRFC(min).To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh

interval is provided. A maximum of eight Refresh commands can be posted, meaning that the maximum absolute interval between

any Refresh command and the next Refresh command is 9 x tREFI.

CLK

COMMAND

CKE = High

PRE

Au t o

Refresh

tRP

tRFC

CMD

Elite Semiconductor Memory Technology Inc.

Publication Date : Mar. 2013

Revision : 1.4

45/59

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