M14D128168A-2M Datasheet, PDF(5/59 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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M14D128168A-2M Datasheet, PDF (5/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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ESMT

M14D128168A (2M)

Operation Temperature Condition

Parameter

Symbol

Value

Unit

Operation temperature

0 ~ +95

Â°C

Note: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.

2. Supporting 0 to +85â with full AC and DC specifications.

Supporting 0 to + 85â and being able to extend to + 95 â with doubling auto-refresh commands in frequency to a

32ms period ( tREFI = 7.9Î¼s ) and higher temperature Self-Refresh entry via A7 â1â on EMRS(2).

DC Operation Condition & Specifications

DC Operation Condition

(Recommended DC operating conditions)

Parameter

Supply voltage

Supply voltage for DLL

Supply voltage for output

Input reference voltage

Termination voltage (system)

Input logic high voltage

Input logic low voltage

(All voltages referenced to VSS)

Symbol

VDD

VDDL

VDDQ

VREF

VTT

VIH (DC)

VIL (DC)

Min.

1.7

0.49 x VDDQ

VREF - 0.04

VREF + 0.125

-0.3

Typ.

1.8

0.5 x VDDQ

VREF

Max.

1.9

0.51 x VDDQ

VREF + 0.04

VDDQ + 0.3

VREF - 0.125

Unit Note

V 4,7

V 1,2,7

V 3,7

Parameter

Symbol

Value

Unit Note

Output minimum source DC current ( VDDQ(min); VOUT

=1.42V )

I OH

-13.4

mA 5,6

Output minimum sink DC current ( VDDQ(min); VOUT =

0.28V )

I OL

+13.4

mA 5,6

Note:

1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of

VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

2. Peak to peak AC noise on VREF may not exceed Â±2% VREF (DC).

3. VTT of transmitting device must track VREF of receiving device.

4. VDDQ and VDDL track VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together.

5. The DC value of VREF applied to the receiving device is expected to be set to VTT.

6. TC = 25â, VDD = VDDQ = 1.8V.

7. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However, under all conditions

VDDQ must be less than or equal to VDD.

Elite Semiconductor Memory Technology Inc.

Publication Date : Mar. 2013

Revision : 1.4

5/59

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