M14D128168A-2M Datasheet, PDF (24/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Burst
Length
4
8
Burst Address Ordering for Burst Length
Starting Column Address
(A2, A1,A0)
Sequential Mode
Interleave Mode
000
0, 1, 2, 3
0, 1, 2, 3
001
1, 2, 3, 0
1, 0, 3, 2
010
2, 3, 0, 1
2, 3, 0, 1
011
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Mode Register Set
0
1
CLK
CLK
2
3
4
5
6
7
8
COMMAND
Precharge
All Banks
tCK
t *2
RP
*1
Mode
Register Set
tMRD
Any
Command
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum t_RP is required to issue MRS command.
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having the DLL disabled for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL
is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Impedance Control
The normal drive strength for all outputs is specified to be SSTL_18. The device also supports a reduced drive strength option,
intended for lighter load and/or point-to-point environments.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
24/59