M14D128168A-2M Datasheet, PDF (58/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
Revision History
Revision
0.1
1.0
1.1
1.2
1.3
1.4
M14D128168A (2M)
Date
2012.05.22
2012.05.30
2012.08.23
2012.09.18
2013.03.11
2013.03.29
Description
Original
Delete "Preliminary"
Add BGA package for A(max) = 1.0mm
Modify the specification of IDD0, IDD1 for speed grade
-2.5 and IDD5
1. Change BGA to VFBGA (Window BGA)
2. Add VFBGA package for A(max) = 1.2mm and 1.0mm
3. Add packing dimension of VFBGA (Window BGA:
8x12.5x1.0mm)
4. Modify the value of A and A1 in packing dimension
( 8x12.5x1.2mm & VFBGA: 8x12.5x1.0mm )
5. Modify Input / Output Capacitance
Modify VFBGA (Window BGA) to FBGA (Window BGA)
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
58/59