M14D128168A-2M Datasheet, PDF (3/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Ball Configuration (Top View)
(FBGA / VFBGA 84, 8mmX12.5mmX1.2mm Body, 0.8mm Ball Pitch)
(FBGA / VFBGA 84, 8mmX12.5mmX1.0mm Body, 0.8mm Ball Pitch)
1
2
3
A ^VDD
NC
VSS
7
VSSQ
8
UDQS
9
VDDQ
B ^{DQ14 VSSQ UDM}
UDQS VSSQ DQ15
C VDDQ DQ9 VDDQ
VDDQ DQ8 VDDQ
D DQ12 VSSQ DQ11
DQ10 VSSQ DQ13
E VDD
NC
VSS
VSSQ LDQS VDDQ
F _{DQ6 VSSQ} LDM
G VDDQ DQ1 VDDQ
LDQS VSSQ DQ7
VDDQ DQ0 _VDDQ
H DQ4 VSSQ DQ3
DQ2 VSSQ DQ5
J ^{VDDL VREF} VSS
K
CKE _WE
L ^{NC BA0 BA1}
VSSDL CLK VDD
RAS CLK ODT
CAS CS
M
A10 A1
N ^VSS
A3
A5
P
A7
A9
R ^{VDD A12}
NC
A2
A0 VDD
A6
A4
A11 A8 VSS
NC NC
Note: A12 (ball R2) is used for MRS/EMRS.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
3/59