M14D128168A-2M Datasheet, PDF (33/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Read Bank
This command is used after the Bank Active command to initiate the burst read of data. The Read command is initiated by
activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table.
The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the Bank Active command to initiate the burst write of data. The Write command is initiated by
activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of
the burst will be determined by the values programmed during the MRS command.
Posted
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In
this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the Bank Active command (or
any time during the t_RRD period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device.
The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W
command before the t_RCD(min), then AL (greater than 0) must be written into the EMRS(1). The Write Latency (WL) is always
defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL).
Read or Write operations using AL allow seamless bursts.
Read followed by a Write to the Same Bank
< AL= 2; CL= 3 ; BL = 4>
CLK
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CMD
Active Read
Bank A Bank A
AL = 2
Write
Bank A
CL = 3
WL = RL -1 =4
DQS/DQS
DQ
>= tRCD
RL = AL + CL = 5
Dout0 Dout1 Dout2 _Dout3
Din0 Din1 Din2 Din3
CLK
CLK
CMD
< AL= 0; CL= 3; BL = 4 >
-1
0
1
2
3
4
5
6
7
8
9
10 11 12
Active
Bank A
AL = 0
Read
Bank A
CL = 3
Write
Bank A
WL = RL -1 = 2
DQS/DQS
DQ
>= tRCD
RL = AL + CL = 3
Dout0 Dout1 Dout2 Dout3
Din0 Din1 Din2 Din3
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
33/59