M14D128168A-2M Datasheet, PDF (47/59 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D128168A (2M)
Power-Down
Power-Down is synchronously entered when CKE is registered LOW (no accesses can be in progress). CKE is not allowed to go
LOW while MRS or EMRS command time, or read or write operation is in progress. CKE is allowed to go LOW while any of other
operations such as Bank Active, Precharge or Auto Precharge, or Auto Refresh is in progress. The DLL should be in a locked state
when Power-Down is entered. Otherwise DLL should be reset after exiting Power-Down mode for proper read operation.
If Power-Down occurs when all banks are idle, this mode is referred to as Precharge Power-Down; if Power-Down occurs when
there is a Bank Active command in any bank, this mode is referred to as Active Power-Down. Entering Power-Down deactivates
the input and output buffers, excluding CLK, CLK , ODT and CKE. Also the DLL is disabled upon entering Precharge Power-Down
or slow exit Active Power-Down, but the DLL is kept enabled during fast exit Active Power-Down. In Power-Down mode, CKE LOW
and a stable clock signal must be maintained at the inputs of the device, and ODT should be in a valid state but all other input
signals are “Don’t Care”. CKE LOW must be maintained until t_CKE has been satisfied. Power-Down duration is limited by 9 times
t_REFI of the device.
The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). CKE
HIGH must be maintained until t_CKE has been satisfied. A valid, executable command can be applied with Power-Down exit latency,
t_XP, t_XARD, or t_XARDS, after CKE goes HIGH.
CLK
CLK
CKE
Command
tIS tIH
tIS tIH
VALID
NOP
tCKE
tCKE
Enter power-down mode
tIH
tIS
tIH
NOP
VALID
VALID
VALID
tXP, tXARD,
tXARDS
Exit power-down mode ^tCKE
: Don’t care
T0
CLK
CLK
T1
T2
Command
CKE
READ
High
BL = 4
DQS
DQS
DQ
T0
CLK
CLK
T1
T2
Command
CKE
READ
High
BL = 8
DQS
DQS
DQ
Read to Power-Down Entry
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CKE should be kept high until the end of burst operation
AL + CL
DoutA0 DoutA1 DoutA2 DoutA3
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CKE should be kept high until the end of burst operation
AL + CL
DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.4
47/59