M14D5121632A-2K Datasheet, PDF (7/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D5121632A (2K)
Parameter
Symbol
Test Condition
Version
Unit
-1.3 -1.5 -1.8 -2.5
t_CK = t_CK (IDD);
Refresh command every t_RFC (IDD) interval;
Auto Refresh Current IDD5 CKE is HIGH, CS is HIGH between valid commands; 140 120 100 100 mA
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
Self Refresh Current
IDD6
CLK and CLK at 0V; CKE  0.2V;
Other control and address bus inputs are FLOATING;
8
mA
Data bus inputs are FLOATING
Operating Current
(Bank interleaving)
All bank interleaving Reads, I_OUT = 0mA;
BL = 4, CL= CL (IDD), AL = t_RCD (IDD) – 1 × t_CK (IDD);
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
IDD7 t_RRD = t_RRD (IDD), t_RCD = 1 × t_CK (IDD);
280 230 210 200 mA
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during Deslects;
Data pattern is the same as IDD4W;
Note:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS and DQS , IDD values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD:
LOW is defined as V_IN  V_IL (AC) (max.).
HIGH is defined as V_IN V_IH (AC) (min.).
STABLE is defined as inputs stable at a HIGH or LOW level.
FLOATING is defined as inputs at V_REF = V_DDQ/2
SWITCHING is defined as:
Address and control signal Inputs are changed between HIGH and LOW every other clock cycle (once per two clocks), and
DQ (not including mask or strobe) signal inputs are changed between HIGH and LOW every other data transfer (once per
clock).
6. When T_C ≧ +85 ℃, IDD6 must be derated by 80%.
IDD6 will increase by this amount if T_C ≧ +85 ℃ and double refresh option is still enabled.
7. AC Timing for IDD test conditions
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
CL (IDD)
tRCD (IDD)
tRC (IDD)
tRRD (IDD)
tCK (IDD)
tRAS (IDD) min.
tRAS (IDD) max.
tRP (IDD)
tRFC (IDD)
-1.3
DDR2-1500
(7-10-10)
7
13.3
80
12
1.333
60
13.3
150
-1.5
-1.8
DDR2-1333
(7-9-9)
DDR2-1066
(7-7-7)
7
7
13.5
13.125
58.125
10
58.125
10
1.5
1.875
45
45
70000
13.5
13.25
130
105
-2.5
DDR2-800
Unit
(5-5-5)
5
t_CK
12.5
ns
57.5
ns
10
ns
2.5
ns
45
ns
ns
12.5
ns
105
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
7/64