M14D5121632A-2K Datasheet, PDF (29/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D5121632A (2K)
Extended Mode Register Set-2 [EMRS(2)]
The EMRS(2) stores the data for enabling or disabling high temperature self refresh rate. The default value of the EMRS(2) is not
defined, therefore EMRS(2) must be written after power up for proper operation. The EMRS(2) is written by asserting LOW on CS ,
RAS , CAS , WE , BA0 and HIGH on BA1 (The device should be in all bank Precharge with CKE already high prior to writing into
EMRS(2)). The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0 going LOW and BA1 going
HIGH are written in the EMRS(2).
The t_MRD time is required to complete the write operation to the EMRS(2). The EMRS(2) contents can be changed using the same
command and clock cycle requirements during normal operation as long as all banks are in the idle state. A7 is used for high
temperature self refresh rate enable or disable.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
0
0^*1
SRF
0^*1
DCC^*2
PASR^*3
BA1 BA0
Mode Register
0 0 MRS
0 1 EMRS(1)
1 0 EMRS(2)
1 1 EMRS(3): Reserved
A7 ^{High Temperature}
Self Refresh rate
0
Disable
1
Enable
A3
DCC Enable
0
Disable
1
Enable
A2 A1 A0
Partial Array Self Refresh
0 0 0 Full Array
0 0 1 Half Array (BA[1:0]=00&01)
0 1 0 Quarter Array (BA[1:0]=00)
0 1 1 Not defined
1 0 0 3/4 Array (BA[1:0]=01, 10&11)
1 0 1 Half Array (BA[1:0]=10&11)
1 1 0 Quarter Array (BA[1:0]=11)
1 1 1 Not defined
*Note:
1. A0~A2, A4~A6 and A8~A12 are reserved for future use and must be set to 0.
2. User may enable or disable the DCC (Duty Cycle Corrector) by programming A3 bit accordingly.
3. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range
will be lost if self refresh is entered. Data integrity will be maintained if t_REF conditions are met and no Self Refresh
command is issued. If the PASR feature is not supported, EMRS(2)[A0-A2] must be set to 000 when programming
EMRS(2).
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
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