M14D5121632A-2K Datasheet, PDF (19/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D5121632A (2K)
Clock Jitter [ DDR2- 1500, 1333, 1066, 800 ]
Parameter
Symbol
Average clock period
Clock period jitter
Clock period jitter during
DLL locking period
Cycle to cycle period jitter
Cycle to cycle clock period
jitter
During DLL locking period
Cumulative error across 2
cycles
Cumulative error across 3
cycles
Cumulative error across 4
cycles
Cumulative error across 5
cycles
Cumulative error across
n=6,7,8,9,10 cycles
Cumulative error across
n=11,12,….49,50 cycles
Average high pulse width
t_CK (avg)
t_JIT (per)
t_JIT (per,lck)
t_JIT (cc)
t_JIT (cc, lck)
t_ERR (2per)
t_ERR (3per)
t_ERR (4per)
t_ERR (5per)
t_ERR
(6-10per)
t_ERR
(11-50per)
t_CH (avg)
-1.3
Min. Max.
1333 3000
-30
30
-30
30
-80
80
-1.5
Min. Max.
1500 3000
-50
50
-40
40
-130 130
-1.8
Min. Max.
1875 7500
-90
90
-80
80
-180 180
-2.5
Min. Max.
2500 8000
-100 100
-80
80
-200 200
-70
70 -120 120 -160 160 -160 160
-50
50 -100 100 -132 132 -150 150
-50
50 -100 100 -157 157 -175 175
-50
50 -100 100 -175 175 -200 200
-50
50 -100 100 -188 188 -200 200
-100 100 -150 150 -250 250 -300 300
-100 100 -150 150 -425 425 -450 450
0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52
Average low pulse width
t_CL (avg)
0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52
Duty cycle jitter
t_JIT (duty)
-30
30
-45
45
-75
75 -100 100
Note:
1. t_CK (avg) is calculated as the average clock period across any consecutive 200 cycle window.
Unit Note
ps
1
ps
5
ps
5
ps
6
ps
6
ps
7
ps
7
ps
7
ps
7
ps
7
ps
7
t_CK
(avg)
2
t_CK
(avg)
3
ps
4
2. t_CH (avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
3. t_CL (avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
4. t_JIT (duty) is defined as the cumulative set of t_CH jitter and t_CL jitter. t_CH jitter is the largest deviation of any single t_CH from t_CH
(avg). t_CL jitter is the largest deviation of any single t_CL from t_CL (avg).
t_JIT (duty) is not subject to production test.
t_JIT (duty) = Min./Max. of { t_JIT (CH), t_JIT (CL)}, where:
t_JIT (CH) = { t_CH j - t_CH (avg) where j =1 to 200}
t_JIT (CL) = {t_CL j - t_CL (avg) where j =1 to 200}
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
19/64