M14D5121632A-2K Datasheet, PDF (57/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D5121632A (2K)
Functional Truth Table ^*7
Current State _{CS RAS CAS WE}
Address
Command
Action
H
X
X
XX
DESEL
NOP or Power-Down
L
H
H
HX
NOP
NOP or Power-Down
IDLE
L
H
L
X BA, CA, A10
L
L
H
H BA, RA
READ / READA
WRITE / WRITEA
/
ILLEGAL (*1)
Active
Bank Active, Latch RA
L
L
H
L BA, A10 / A10
PRE / PREA
Precharge / Precharge All
L
L
L
HX
Refresh
Refresh (*2)
L
L
L
L Op-Code Mode-Add MRS / EMRS
Mode Register setting / Extended
Mode Register setting (*2)
H
X
X
XX
DESEL
NOP
L
H
H
HX
NOP
NOP
L
H
L
H BA, CA, A10
READ / READA
Begin Read, Latch CA,
Determine Auto Precharge
BANK ACTIVE ^L
H
L
L BA, CA, A10
WRITE / WRITEA
Begin Write, Latch CA,
Determine Auto Precharge
L
L
H
H BA, RA
Active
ILLEGAL (*1)
L
L
H
L BA, A10 /A10
PRE / PREA
Precharge / Precharge All
L
L
L
HX
Refresh
ILLEGAL
L
L
L
L Op-Code Mode-Add MRS / EMRS
ILLEGAL
H
X
X
XX
DESEL
NOP (Continue Burst to END)
L
H
H
HX
NOP
NOP (Continue Burst to END)
READ
L
H
L
H BA, CA, A10
L
H
L
L BA, CA, A10
READ / READA
WRITE / WRITEA
Terminate Burst, Latch CA,
Begin New Read,
Determine Auto Precharge (*1, 4)
ILLEGAL (*1)
L
L
H
H BA, RA
Active
ILLEGAL (*1)
L
L
H
L BA, A10 / A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
L
L
L
HX
Refresh
ILLEGAL
L
L
L
L Op-Code Mode-Add MRS / EMRS
ILLEGAL
H
X
X
XX
DESEL
NOP (Continue Burst to end)
L
H
H
HX
L
H
L
H BA, CA, A10
NOP
READ / READA
NOP (Continue Burst to end)
ILLEGAL (*1)
WRITE
L
H
L
L BA, CA, A10
L
L
H
H BA, RA
WRITE / WRITEA
Active
Terminate Burst, Latch CA,
Begin new Write,
Determine Auto-Precharge (*1, 4)
ILLEGAL (*1)
L
L
H
L BA, A10 / A10
PRE / PREA
ILLEGAL (*1) / ILLEGAL
L
L
L
HX
Refresh
ILLEGAL
L
L
L
L Op-Code Mode-Add MRS / EMRS
ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
57/64