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M14D5121632A-2K Datasheet, PDF (16/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle
ESMT
M14D5121632A (2K)
AC Timing Parameter & Specifications - Contiuned
Parameter
Symbol
-1.8
Min.
Max.
-2.5
Min.
Max.
Unit Note
Minimum time clocks remains
ON after CKE asynchronously
drops low
tDELAY
tIS + tCK
(avg)+tIH
tIS + tCK
(avg)+tIH
ns
Output impedance test driver
delay
tOIT
0
12
0
12
ns
MRS command to ODT update
delay
tMOD
0
12
0
12
ns
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down
mode)
ODT to Power-Down entry
latency
tAOND
2
2
2
2
tCK
tAON
tAC(min.)
tAC(max.) +
2575
tAC(min.)
tAC(max.) +
700
ps
14,16
tAONPD
tAC(min.) +
2000
3 x tCK
+tAC(max.) +
1000
tAC(min.) +
2000
2 x tCK
+tAC(max.) +
1000
ps
tAOFD
2.5
2.5
2.5
2.5
tCK
15,17,
18
tAOF
tAC(min.)
tAC(max.) +
600
tAC(min.)
tAC(max.) +
600
ps
tAOFPD
tAC(min.) +
2000
2.5 x tCK
+tAC(max.) +
1000
tAC(min.) +
2000
2.5 x tCK
+tAC(max.) +
1000
ps
tANPD
4
3
tCK
ODT Power-Down exit latency
tAXPD
11
8
tCK
Note:
1. tDAL[nCLK] = WR[nCLK] + tnRP [nCLK] =WR+RU{tRP[ps]/tCK(avg)[ps]}, where WR is the value programmed in the mode
register set and RU status for round up.
2. AL: Additive Latency.
3. MRS A12 bit defines which Active Power-Down Exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a rising
signal and VIL (AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a rising
signal and VIH (DC) for a falling signal applied to the device under test.
6. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input
specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH
calculation is determined by the following equation;
tHP = Min ( tCH (abs), tCL (abs) ), where:
tCH (abs) is the minimum of the actual instantaneous clock HIGH time;
tCL (abs) is the minimum of the actual instantaneous clock LOW time;
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
16/64