M14D5121632A-2K Datasheet, PDF (13/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D5121632A (2K)
AC Timing Parameter & Specifications - Contiuned
Parameter
Minimum time clocks remains
ON after CKE asynchronously
drops low
Output impedance test driver
delay
MRS command to ODT update
delay
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
mode)
Symbol
-1.3
Min.
Max.
t_DELAY
t_IS + t_CK
(avg)*2+t_IH
t_OIT
0
12
t_MOD
t_AOND
t_AON
t_AONPD
0
12
2
t_AC(min.)
t_AC(min.) +
2000
2
t_AC(max.) +
700
2 x t_CK
+t_AC(max.) +
1000
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down
mode)
ODT to Power-Down entry
latency
ODT Power-Down exit latency
t_AOFD
t_AOF
t_AOFPD
t_ANPD
t_AXPD
5
t_AC(min.)
t_AC(min.) +
2000
5
5
t_AC(max.) +
600
2.5 x t_CK
+t_AC(max.) +
1000
10
-1.5
Min.
Max.
t_IS + t_CK
(avg)+t_IH
0
12
0
12
2
t_AC(min.)
t_AC(min.) +
2000
2
t_AC(max.) +
2575
3 x t_CK
+t_AC(max.) +
1000
2.5
2.5
t_AC(min.)
t_AC(min.) +
2000
t_AC(max.) +
600
2.5 x t_CK
+t_AC(max.) +
1000
4
11
Unit Note
ns
ns
ns
t_CK
ps
14,16
ps
t_CK
15,17,
18
ps
ps
t_CK
t_CK
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
13/64