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M14D5121632A-2K Datasheet, PDF (11/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle
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ESMT
M14D5121632A (2K)
AC Timing Parameter & Specifications
Parameter
Symbol
-1.3
Min.
Max.
Clock period
CL=7
DQ output access time from
CLK/ CLK
tCK (avg)
tAC
1333
-400
3000
+400
CLK high-level width
CLK low-level width
DQS output access time from
CLK/ CLK
tCH (avg)
tCL (avg)
tDQSCK
0.48
0.48
-350
0.52
0.52
+350
Clock to first rising edge of DQS
delay
Data-in and DM setup time
(to DQS)
tDQSS
tDS
(base)
-0.25
200
+0.25
Data-in and DM hold time
(to DQS)
DQ and DM input pulse width
(for each input)
Address and Control Input
setup time
tDH
(base)
tDIPW
tIS (base)
200
0.35
125
Address and Control Input hold
time
tIH (base)
Control and Address input pulse
width
tIPW
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS falling edge to CLK rising
setup time
tDSS
DQS falling edge from CLK
rising hold time
tDSH
250
0.6
0.35
0.35
0.2
0.2
Data strobe edge to output data
edge
tDQSQ
200
Data-out high-impedance
window from CLK/ CLK
tHZ
tAC(max.)
Data-out low-impedance window tLZ
from CLK/ CLK
(DQS)
tAC(min.)
tAC(max.)
DQ low-impedance window from
CLK/ CLK
Half clock period
DQ/DQS output hold time from
DQS
tLZ
(DQ)
tHP
tQH
2 x tAC(min.)
Min
(tCL(abs),tCH(a
bs))
tHP-tQHS
tAC(max.)
DQ hold skew factor
tQHS
300
-1.5
Min.
Max.
1500
3000
-350
+350
0.48
0.52
0.48
0.52
-300
+300
-0.25
200
200
0.35
125
200
0.6
0.44
0.44
0.2
0.2
+0.25
250
tAC(max.)
tAC(min.)
tAC(max.)
2 x tAC(min.) tAC(max.)
Min
(tCL(abs),tCH(a
bs))
tHP-tQHS
250
Unit Note
ps
13
ps
10
tCK (avg) 13
tCK (avg) 13
ps
10
tCK (avg)
ps
4
ps
5
tCK (avg)
ps
4
ps
5
tCK (avg)
tCK (avg)
tCK (avg)
tCK (avg)
tCK (avg)
ps
ps
10
ps
10
ps
10
ps
6,13
ps
ps
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
11/64
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