M14D5121632A-2K Datasheet, PDF(23/64 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

M14D5121632A-2K Datasheet, PDF (23/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

◁

ESMT

M14D5121632A (2K)

Slew Rate Definition Tangent

Elite Semiconductor Memory Technology Inc.

Publication Date : May 2014

Revision : 1.4

23/64

▷