M14D5121632A-2K Datasheet, PDF(6/64 Page) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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M14D5121632A-2K Datasheet, PDF (6/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

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ESMT

M14D5121632A (2K)

DC Specifications

(IDD values are for the operation range of Voltage and Temperature)

Parameter

Symbol

Test Condition

Version

Unit

-1.3 -1.5 -1.8 -2.5

One bank;

Operating Current

(Active - Precharge)

IDD0

tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS (IDD)min;

CKE is High, CS is HIGH between valid commands;

130 100 80

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

One bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

Operating Current

tCK = tCK (IDD), tRC = tRC (IDD),

(Active - Read -

IDD1 tRAS = tRAS (IDD)min, tRCD = tRCD (IDD);

160 130 100 95 mA

Precharge)

CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Precharge

Power-Down

Standby Current

IDD2P

All banks idle;

tCK = tCK (IDD); CKE is LOW;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

18 15 12 12 mA

Precharge Quiet

Standby Current

IDD2Q

All banks idle;

tCK = tCK (IDD); CKE is HIGH, CS is HIGH;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

80 60 40 40 mA

All banks idle;

Idle Standby Current IDD2N

tCK = tCK (IDD); CKE is HIGH, CS is HIGH;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Active Power-down

Standby Current

IDD3P

All banks open;

tCK = tCK (IDD); CKE is LOW;

Other control and address bus inputs

are STABLE;

Data bus input are FLOATING

Fast PDN Exit

MRS(12) = 0

Slow PDN Exit

MRS(12) = 1

All banks open;

Active Standby

Current

tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD);

IDD3N CKE is HIGH, CS is HIGH between valid commands; 80 60 50 50 mA

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

All banks open, continuous burst Reads, IOUT = 0mA;

BL = 4, CL = CL (IDD), AL = 0;

Operation Current

(Read)

IDD4R

tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD);

CKE is HIGH, CS is HIGH between valid commands;

200 180 160 140

Address bus inputs are SWITCHING;

Data pattern is the same as IDD4W;

All banks open, continuous burst Writes;

BL = 4, CL = CL (IDD), AL = 0;

Operation Current

(Write)

IDD4W

tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD);

CKE is HIGH, CS is HIGH between valid commands;

190 170 150 130

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Elite Semiconductor Memory Technology Inc.

Publication Date : May 2014

Revision : 1.4

6/64

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