M14D5121632A-2K Datasheet, PDF (50/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D5121632A (2K)
tRC Limit
< RL= 5 (AL= 2; CL= 3); BL= 4; tRCD = 3 clocks; tRTP <= 2 clocks >
T0
T1
T2
T3
T4
T5
T6
T7
CLK
CLK
CMD
Posted CAS
READ A
Autoprecharge
DQS,DQS
DQs
AL = 2
NOP
NOP
>= tRAS(min)
RL = 5
CL = 3
NOP
NOP
Autoprecharge begins
NOP
NOP
NOP
>= tRP
DoutA0 DoutA1 DoutA2 DoutA3
T8
Bank A
Active
tRP Limit
CLK
CLK
CMD
Posted CAS
READ A
Autoprecharge
DQS,DQS
DQs
AL = 2
NOP
NOP
>= tRAS(min)
RL = 5
CL = 3
>= tRC
NOP
NOP
Autoprecharge begins
NOP
NOP
Bank A
Active
>= tRP
DoutA0 DoutA1 DoutA2 DoutA3
NOP
>= tRC
Write with Auto Precharge
If A10 is HIGH when a Write command is issued, the Write with Auto Precharge function is engaged (If t_CK < 1.875ns, the device
can not support Write with Auto Precharge function). The device automatically begins precharge operation after the completion of
the burst write plus write recovery time (t_WR). The Bank Active command undergoing Auto Precharge from the completion of the
write burst may be reactivated if the following two conditions are satisfied.
(1) The data-in to bank activate delay time (t_WR + t_RP) has been satisfied.
(2) The RAS cycle time (t_RC) from the previous bank activation has been satisfied.
< WR = 2; BL= 4; tRP = 3 clocks >
T0
T1
T2
T3
T4
T5
T6
T7
Tm
CLK
CLK
tRC Limit
CMD
Posted CAS
WRITE A
Autoprecharge
NOP
DQS,DQS
WL = RL-1 = 2
NOP
NOP
NOP
NOP
NOP
NOP
Auto Precharge begins
>= tWR
>= tRP
Bank A
Active
DQs
DinA0 DinA1 DinA2 DinA3
>= tRC
T0
T3
T4
T5
T6
T7
T8
T9
T12
CLK
CLK
tWR + tRP
CMD
Posted CAS
WRITE A
Autoprecharge
DQS,DQS
NOP
NOP
WL = RL-1 = 4
NOP
NOP
NOP
NOP
NOP
Auto Precharge begins
>= tWR
>= tRP
Bank A
Active
DQs
DinA0 DinA1 DinA2 DinA3
>= tRC
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
50/64