M14D5121632A-2K Datasheet, PDF (55/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D5121632A (2K)
Write with Auto Precharge to Power-Down Entry
T0
CLK
CLK
Command
T1
Tm
WRITE A
Tm+1
Tm+2
Tm+3
Tx
Tx+1
Tx+2
PRE
CKE
BL = 4
DQS
DQS
DQ
WL
DinA0 DinA1 DinA2 DinA3
tWR
T0
CLK
CLK
T1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tx
Command
WRITE A
Tx+3
Tx+4
Tx+1
Tx+2
PRE
Tx+5
Tx+3
Tx+6
Tx+4
CKE
BL = 8
DQS
DQS
DQ
WL
DinA0 DinA1 DinA2 DinA3 DinA4 DinA5 DinA6 DinA7
tWR
Note: If t_CK < 1.875ns, the device can not support Write with Auto Precharge function.
Auto Refresh/ Bank Active/ Precharge to Power-Down Entry
T0
CLK
CLK
Command
CKE
T1
T2
T3
T4
T5
T6
CMD
CKE can go to low one clock after a command
T7
T8
T9
T10
T11
Note: CMD could be Auto Refresh/ Bank Active/ Precharge command.
MRS/EMRS to Power-Down Entry
T0 T1
T2
T3
CLK
CLK
Command
MRS/
EMRS
CKE
tMRD
T4 T5
T6 T7
T8
T9
T10
T11
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
55/64