M14D5121632A-2K Datasheet, PDF (14/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
M14D5121632A (2K)
AC Timing Parameter & Specifications - Contiuned
Parameter
Symbol
-1.8
Min.
Max.
CL=7
1875
7500
Clock period
CL=6 _{tCK (avg)}
X
X
CL=5
X
X
CL=4
X
X
DQ output access time from
CLK/ CLK
t_AC
-350
+350
CLK high-level width
CLK low-level width
DQS output access time from
CLK/ CLK
t_CH (avg)
t_CL (avg)
t_DQSCK
0.48
0.48
-300
0.52
0.52
+300
Clock to first rising edge of DQS
delay
t_DQSS
-0.25
+0.25
Data-in and DM setup time
(to DQS)
t_DS
(base)
0
Data-in and DM hold time
(to DQS)
t_DH
(base)
75
DQ and DM input pulse width
(for each input)
t_DIPW
0.35
Address and Control Input
setup time
t_IS (base)
125
Address and Control Input hold
time
t_IH (base)
200
Control and Address input pulse
width
t_IPW
0.6
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising
setup time
t_DQSH
t_DQSL
t_DSS
0.35
0.35
0.2
DQS falling edge from CLK
rising hold time
t_DSH
0.2
Data strobe edge to output data
edge
t_DQSQ
175
Data-out high-impedance
window from CLK/ CLK
t_HZ
t_AC(max.)
Data-out low-impedance window tLZ
from CLK/ CLK
(DQS)
t_AC(min.)
t_AC(max.)
DQ low-impedance window from
CLK/ CLK
Half clock period
t_LZ
(DQ)
t_HP
2 x t_AC(min.)
Min
(t_CL(abs),t_CH(a
bs))
t_AC(max.)
-2.5
Min.
Max.
-
-
2500
8000
2500
8000
X
X
-400
+400
0.48
0.52
0.48
0.52
-350
+350
-0.25
50
125
0.35
175
250
0.6
0.35
0.35
0.2
0.2
+0.25
200
t_AC(max.)
t_AC(min.)
t_AC(max.)
2 x t_AC(min.) t_AC(max.)
Min
(t_CL(abs),t_CH(a
bs))
Unit Note
ps
13
ps
10
t_CK (avg) 13
t_CK (avg) 13
ps
10
t_CK (avg)
ps
4
ps
5
t_CK (avg)
ps
4
ps
5
t_CK (avg)
t_CK (avg)
t_CK (avg)
t_CK (avg)
t_CK (avg)
ps
ps
10
ps
10
ps
10
ps
6,13
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
14/64