M14D5121632A-2K Datasheet, PDF (12/64 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture; two data access per clock cycle

ESMT
AC Timing Parameter & Specifications - Contiuned
Parameter
Symbol
Active to Precharge command
Active to Active command
(same bank)
Auto Refresh row cycle time
Active to Read, Write delay
Precharge command period
Active bank A to Active bank B
command
Write recovery time
Write data in to Read command
delay
Col. address to Col. address
delay
Average periodic Refresh
interval ( 0℃ ≦T_C ≦ +85℃ )
Average periodic Refresh
interval (+85℃ ＜T_C ≦ +95℃)
Write preamble
Write postamble
DQS Read preamble
DQS Read postamble
Load Mode Register / Extended
Mode Register cycle time
Auto Precharge write recovery
+ Precharge time
Internal Read to Precharge
command delay
Exit Self Refresh to Read
command
Exit Self Refresh to non-Read
command
Exit Precharge Power-Down to
any non-Read command
Exit Active Power-Down to
Read command
Exit active power-down to Read
command
(slow exit / low power mode)
CKE minimum pulse width
(high and low pulse width)
t_RAS
t_RC
t_RFC
t_RCD
t_RP
t_RRD
t_WR
t_WTR
t_CCD
t_REFI
t_REFI
t_WPRE
t_WPST
t_RPRE
t_RPST
t_MRD
t_DAL
t_RTP
t_XSRD
t_XSNR
t_XP
t_XARD
t_XARDS
t_CKE
-1.3
Min.
Max.
60
70K
80
150
13.3
13.3
12
15
7.5
4
7.8
3.9
0.35
0.4
0.6
0.9
1.1
0.4
0.6
2
X
10
200
t_RFC + 10
5
5
12 - AL
5
M14D5121632A (2K)
-1.5
Min.
Max.
45
70K
58.125
130
13.5
13.5
10
15
7.5
2
7.8
3.9
0.35
0.4
0.6
0.9
1.1
0.4
0.6
5
-X
7.5
200
t_RFC + 10
5
5
10 - AL
5
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
19
t_CK
us
us
t_CK (avg)
t_CK (avg)
t_CK (avg)
11
t_CK (avg) 12
t_CK
t_CK
1, 20
ns
t_CK
ns
t_CK
t_CK
3
t_CK
2,3
t_CK
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2014
Revision : 1.4
12/64