M13L32321A-2G Datasheet, PDF (7/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
IDD Specifications
Symbol
-5
IDD0
125
IDD1
145
IDD2P
9
IDD2F
85
IDD2Q
85
IDD3P
20
IDD3N
105
IDD4R
200
IDD4W
200
IDD5
180
IDD6
3
IDD7
250
Version
-6
115
135
9
85
85
20
105
190
190
170
3
240
M13L32321A (2G)
Unit
-7.5
105
mA
125
mA
9
mA
85
mA
85
mA
20
mA
105
mA
180
mA
180
mA
160
mA
3
mA
230
mA
Input / Output Capacitance
(V_DD = 3.3V ± 0.3V, V_DDQ = 3.3V ± 0.3V, T_A = 25 °C , f = 1MHz)
Parameter
Symbol Min
Input capacitance (A0~A10, BA, CKE, CS ,
C_IN1
1
RAS , CAS , WE )
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
C_IN2
1
C_OUT
1
C_IN3
1
Max
Unit
4.5
pF
5
pF
6.5
pF
6.5
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
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