M13L32321A-2G Datasheet, PDF (32/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13L32321A (2G)
Multi Bank Interleaving READ (@ BL=4, CL=2)
0
1
CLK
CLK
CKE
2
3
4
5
6
7
8
9
10
HIGH
CS
RAS
CAS
BA
A8/AP
Ra
Rb
ADDR
Ra
(A0~A7, A9)
Rb
Ca
Cb
WE
DQS
DQ
DM
COMMAND
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
ACTIVE
tRCD
tRRD
ACTIVE
READ
tCCD
READ
: Don’t care
1110 1B3 2R.A
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
32/48