 English |
|
|
|
|
|
|
|
| M13L32321A-2G Datasheet, PDF (4/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle | |||
| |||
| ◁ |
ESMT
M13L32321A (2G)
Absolute Maximum Rating
Parameter
Voltage on VDD & VDDQ supply relative to VSS
Voltage on inputs relative to VSS
Voltage on I/O pins relative to VSS
Operating ambient temperature
Storage temperature
Power dissipation
Short circuit current
Symbol
VDD, VDDQ
VINPUT
VIO
TA
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-0.5 ~ VDDQ+0.5
0 ~ +70
-55 ~ +150
2
50
Unit
V
V
V
°C
°C
W
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Symbol
VDD
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
VIN (DC)
Min
3
3
0.49*VDDQ
VREF - 0.04
VREF + 0.6
-0.3
-0.3
Input Differential Voltage, CLK and CLK inputs VID (DC)
0.36
VâI Matching: Pullup to Pulldown Current Ratio VI (Ratio)
0.71
Input leakage current: Any input 0V ⤠VIN ⤠VDD
(All other pins not tested under = 0V)
IL
-2
Output leakage current
(DQs are disable; 0V ⤠VOUT ⤠VDDQ)
IOZ
-5
Max
3.6
3.6
0.51*VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.6
VDDQ + 0.3
VDDQ + 0.6
1.4
2
5
Unit Note
V
V
V
1
V
2
V
V
V
V
3
-
4
μA
μA
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
4/48
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese