M13L32321A-2G Datasheet, PDF (23/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13L32321A (2G)
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access
is allowed. A write recovery time (t_WR) is required from the last data to precharge command. When precharge command is asserted,
any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
0
1
CLK
CLK
2
3
4
5
6
7
8
COMMAND
DQS
NOP
WRITE A
NOP
Hi-Z
tDQSS(max)
NOP
NOP
NOP
tWR
Precharge A W RITE B
DQ's
Hi-Z
tWPRES ^*5
DINA0 DINA1 DINA2 DINA3 _DINA4 DINA5 DINA6 DINA7
NOP
DINB0
DM
DQS
DQ's
Hi-Z
Hi-Z
tDQSS(min)
tWR
tWPRES *5
DINA0 DINA1 DINA2 DINA3 _DINA4 DINA5 DINA6 DINA7
DINB0 DINB1
DM
Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the time required by a DRAM
core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, t_WR, is used to indicate
the required of time between the last valid write operation and a Precharge command to the same bank.
t_WR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge that
strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by t_WR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time
between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input
is still required to strobe in the state of DM. The minimum time for write recovery is defined by t_WR.
3. For a Write with auto precharge command, a new Bank Activate command may be issued to the same bank after t_WR + t_RP where t_WR
+ t_RP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank
Activate commands. During write with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest
possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless t_RAS(min) [minimum Bank Activate to Precharge time] has been satisfied.
This includes Write with auto precharge commands where t_RAS(min) must still be satisfied such that a Write with auto precharge
command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt
the burst.
5. Refer to “Burst write operation”
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
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