M13L32321A-2G Datasheet, PDF (33/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13L32321A (2G)
Multi Bank Interleaving WRITE (@ BL=4)
0
1
CLK
CLK
CKE
2
3
4
5
6
7
8
HIGH
9
10
CS
RAS
CAS
BA
A8/AP
Ra
Rb
ADDR
(A0~A7, A9)
Ra
Rb
Ca
Cb
WE
DQS
DQ
DM
COMMAND
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
ACTIVE
tRCD
ACTIVE
tRRD
WRITE
tRCD
tCCD
WRITE
: Don’t care
1110 1 B3 2 R.A
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
33/48