M13L32321A-2G Datasheet, PDF (44/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Mode Register Set
CLK
CLK
0
1
2
3
4
5
6
CKE
tMRD
HIGH
CS
RAS
CAS
WE
BA
A8/AP
ADDR
(A0~A7, A9)
ADDRESS KEY
DS
DQ
DQS
tRP
High-Z
High-Z
Precharge
Command
All Bank
Mode Register Set
Command
Any
Command
Note: Power & Clock must be stable for 200us before precharge all banks.
M13L32321A (2G)
7
8
9
10
: Don’t care
111 0 1 B 3 2 R . A
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
44/48