M13L32321A-2G Datasheet, PDF (42/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
DM Function (@ BL=8) only for write
0
1
CLK
CLK
2
3
4
5
6
CKE
HIGH
CS
RAS
CAS
BA
A8/AP
ADDR
(A0~A7, A9)
Ca
WE
DQS
DQ
DM
COMMAND
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
WRITE
M13L32321A (2G)
7
8
9
10
: Don’t care
111 0 1 B 3 2 R . A
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
42/48