M13L32321A-2G Datasheet, PDF (40/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Read Interrupted by a Write & Burst Terminate (@ BL=8, CL=2)
0
1
CLK
CLK
2
3
4
5
6
CKE
HIGH
CS
RAS
CAS
BA
A8/AP
ADDR
(A0~A7, A9)
Ca
Cb
WE
M13L32321A (2G)
7
8
9
10
DQS
DQ
DM
COMMAND
Qa0 Qa1
Db0 Db1 Db2 Db3 Db4 db5 Db6 Db7
READ
Burst
Terminate
WRITE
: Don’t care
1110 1B3 2R. A
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
40/48