M13L32321A-2G Datasheet, PDF (17/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13L32321A (2G)
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each
bank respectively or all banks simultaneously. The bank select address (BA) is used to define which bank is precharged when the
command is initiated. For write cycle, t_WR(min) must be satisfied until the precharge command can be issued. After t_RP from the
precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by bank address bits
A8/AP
BA
Precharge
0
0
Bank A Only
0
1
Bank B Only
1
X
All Banks
No Operation & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs.
The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and
NOP the device should finish the current operation when this command is issued.
Bank / Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock
(CLK). The DDR SDRAM has two independent banks, so Bank Select address (BA) is required. The Bank Activation command must
be applied before any Read or Write operation is executed. The Bank Activation command to the first Read or Write command must
meet or exceed the minimum of RAS to CAS delay time (t_RCDRD or t_RCDWR min). Once a bank has been activated, it must be
precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between
interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t_RRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
0
1
CLK
CLK
2
3
Tn
Tn+1
Tn+2
Address
Bank A
Row Addr.
Command
Bank A
Activate
Bank A
Col. Addr.
RAS-CAS delay (tRCDWR)
NOP
NOP
Write A
with AP
ROW Cycle Time (tRC)
Bank B
Row Addr.
Bank A
Row. Addr.
RAS-RAS delay (tRRD)
Bank B
Activate
NOP
Bank A
Activate
: Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
17/48